Charge transfer device with booster circuit

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United States of America Patent

PATENT NO 4984256
SERIAL NO

07152382

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A floating diffusion region and a drain region are formed separately from each other in a substrate. A reset electrode is arranged above an area located between the drain region and the floating diffusion region. A voltage step-up circuit having a reference voltage generator receiving a power source voltage for generating a reference voltage and a step-up circuit receiving a clock pulse for applying a voltage level of the clock pulse to the reference voltage applies a voltage to the drain region. The gate of a conversion E type MOS transistor for converting and outputting the charge stored in the floating diffusion region to a signal having a voltage level proportional to the charge amount is connected to the floating diffusion region. The reference voltage generator has D type MOS transistor and E type MOS transistor connected in cascade for producing the reference voltage of the value corresponding to the variation from a process center of the manufacturing process of this charge transfer device. The D type MOS transsitor has the same conductivity type and construction as the MOS transistor formed of the reset electrode, the floating diffusion region and the drain region. The E type MOS transistor has the same conductivity type as the conversion E type MOS transistor.

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Patent Owner(s)

  • KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Imai, Shin-ichi Yokohama, JP 38 172

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