Method of assembling stacks of integrated circuit dies

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 4984358
SERIAL NO

07539769

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Integrated circuit dies, while still in wafer form, are prepared for stacking without requiring packaging. Holes are made through a wafer having a plurality of integrated circuit dies and are placed between the dies and adjacent the die pads. A layer of insulating material is placed on the wafer and in the outer periphery of the holes. An electrically conductive connection is made between the top of each pad and the inside of the insulating material in an adjacent hole. The insulating layer and the electrically conductive layer can be further extended to the backside of the dies if desired. The dies are separated from each other and can be assembled in a stack and/or surface mounted to a substrate.

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Patent Owner(s)

Patent OwnerAddress
SAMSUNG ELECTRONICS CO LTDSUWON-SI GYEONGGI-DO 16677

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nelson, Bradley H Austin, TX 2 237

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