Output buffer semiconductor and method for controlling current flow in an output switching device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 15, 1991
Grant Date -
N/A
app pub date -
Nov 22, 1988
filing date -
Nov 26, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An output buffer circuit comprises a NAND circuit and a NOR circuit each receiving an output a of a signal source and an output b of an output control circuit and an output driving circuit formed by a p channel MOS transistor and an n channel MOS transistor receiving outputs of the NAND circuit and the NOR circuit. Large output capacitance is connected to an output of the output driving circuit. The n channel MOS transistor is connected between the output of the NOR circuit and a ground potential, and has its gate receiving the output of the output driving circuit. When the output of the output driving circuit is at an 'H' level, the rise of the output of the NOR circuit is controlled, so that the output of the output driving circuit is first changed to the 'L' level slowly. Therefore, discharge current from the output capacitance rises slowly. However, since transconductance of the n channel MOS transistor in the output driving circuit is set large, the output of the output driving circuit falls rapidly from halfway.
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