Binary adder circuit with improved inputs
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United States of America Patent
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Jan 15, 1991
Grant Date -
N/A
app pub date -
Sep 23, 1988
filing date -
Sep 23, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A binary calculation circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced.
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