Method for assembling, testing, and packaging integrated circuits
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United States of America Patent
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-
Jan 22, 1991
Grant Date -
N/A
app pub date -
Nov 3, 1989
filing date -
Nov 3, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An assembly flow in which integrated circuits are burned-in and parametrically tested before assembly is provided. The integrated circuits are sorted based on the results of the parametric testing, and assembled in groups with similar parameters. Integrated circuits from a single group are assembled on a leadframe and encapsulated, marked, and tested again while still attached to the leadframe. Finally, the packaged integrated circuits are separated from the leadframe and those meeting predetermined parameters are loaded into carrier sleeves.
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