Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
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United States of America Patent
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Feb 12, 1991
Issued Date -
N/A
app pub date -
Apr 23, 1990
filing date -
Jul 1, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to proceed in parallel.
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