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Abstract

Method and apparatus for testing the address/data paths between the ROM and CPU of a computer where the computer includes a first connector adapted to connect the ROM to the address/data paths so that data can be transferred between the CPU and the ROM via the data paths of the address/data paths and a second connector adapted to connect the CPU to the address/data paths so that addresses can be applied to an address decoder for the ROM via the address lines of the address/data paths. A memory is connected to the address decoder and the data lines via the first connector, the memory storing predetermined data at a plurality of memory locations. A kernel debugging module connected to the address/data paths via the second connector includes circuitry for successively applying read signals which emulate those provided by the CPU to successively read the predetermined data stored at the memory locations. Comparison circuitry is also provided for successively comparing (i) the predetermined data as it occurs at at least one selected node of the tested address/data paths with (ii) the same data as it occurs at the selected node in address/data paths known to be fault free until all of the predetermined data has been read to thus determine if the tested address/data paths are fault free at the selected node. Also disclosed are ROM function, stuck lines, and memory map routines.

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First Claim