Semiconductor memory device

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United States of America Patent

PATENT NO 4996671
SERIAL NO

07481057

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Abstract

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A semiconductor memory device of the present invention includes bit lines and common data lines for data writing or readout into or from plural memory cells. On these bit lines and common data lines, equalizing or precharging circuits are provided and operate during address transition. During transition from writing to readout, such transition is detected to actuate the equalizing or precharging circuits more promptly than usual to shorten the write recovery time to realize a high speed operation. The output circuit of the semiconductor memory device of the present invention is provided with a precharging circuit for sensing and precharging the level on the output terminal to an intermediate level. The output circuit of this construction allows to reduce the power consumption and to assure a high speed outputting operation.

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Patent Owner(s)

Patent OwnerAddress
KANAGAWA JAPAN7-35 KITASHINAGAWA-6 SHINAGAWA-KU A CORP OF JAPAN TOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Araki, Shigeo Kanagawa, JP 28 342
Suzuki, Hiroyuki Kanagawa, JP 847 10497

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