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Abstract

Semiconductor memory device including a dynamic memory array having a plurality of dynamic memory cells arranged in a matrix of rows and columns, write line and read line buffer memories disposed at the input and output of the dynamic memory array, and internal control circuitry including an internal refresh circuit and an internal arbiter circuit for determining relative priority as between write, read, and refresh request signals such that the internal refresh circuit is enabled to generate a refresh request signal for periodically applying a refresh signal to the dynamaic memory cells of the dynamic memory array without requiring an external control signal for implementation of the refresh request signal. In a particular aspect, the write line buffer memory and the read line buffer memory are respectively divided into first and second sections for alternate tandem operation in relation to one-half row of dynamic memory cells of the dynamic memory array so as to provide for continuous serial data input to the dynamic memory array via the alternate tandem operation of the first and second write line buffer memory sections and continuous serial data output from the dynamic memory array without interruption from the refresh mode during its operation cycle via the alternate tandem operation of the first and second read line buffer memory sections with respect to one-half row of dynamic memory cells of the dynamic memory array.

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First Claim