Central processing unit with improved stack register operation
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United States of America Patent
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-
Mar 19, 1991
Grant Date -
N/A
app pub date -
Sep 25, 1987
filing date -
Jan 27, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a central processing unit, one write address is made to correspond to a pair of registers, and when an instruction output from an instruction decoder is a data transfer instruction to either one of the above-mentioned pair of registers, the data held in one of the above-mentioned pair of registers is kept to be held in either register of the above-mentioned pair of registers and the data from the internal data bus is transferred to the remaining register of the pair of registers, and in response to a read instruction, data is transferred from each register to the internal data bus without changing the contents of the other register.
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