Integrated CPU and DMA with shared executing unit

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United States of America Patent

PATENT NO 5005121
SERIAL NO

07326472

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Abstract

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A data processor controller for a microprogramming system is constructed with a single operation execution unit serving both a microprocessor and a peripheral device such as a direct memory access controller. In addition to the single operation execution unit, the controller includes a micro-memory which stores micro-instructions for controlling both the microprocessor and the peripheral device, and address registers, multiplexers and decoders integrated into a single device. Different ROM address registers in the controller are separately assigned to provide an address decoder with addresses of selected memory locations in the micro-memory containing the micro-instructions for the microprocessor and the peripheral device, thereby enabling the controller, through multiplexing between the address registers, to use the arithmetic execution unit, counter and bus interface of the single operation exeuction unit on a time sharing basis, for controlling the functions of both the microprocessor and the peripheral device.

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Patent Owner(s)

Patent OwnerAddress
HITACHI LTD A CORP OF JAPAN6 KANDA SURUGADAI 4-CHOME CHIYODA-KU TOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Akao, Yasushi Kokubunji, JP 58 1723
Nakada, Kunihiko Kodaira, JP 14 185

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