Method and apparatus for checksum address generation in a fail-safe modular memory
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United States of America Patent
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Apr 9, 1991
Grant Date -
N/A
app pub date -
Nov 30, 1988
filing date -
Nov 30, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A modular fail-safe memory and an address generation mechanism that provides load balancing when the memory is shared by a number of processors. A plurality of memory modules are used for the memory with no specific limit on the number of memory modules, and a checksum block is used to back-up corresponding blocks in the other memory modules. The checksum blocks are distributed across the memory modules, and an address generation mechanism determines the checksum location for a specific memory block. This address generation mechanism ensures that checksum blocks are equally divided between the memory modules so that there is no memory bottleneck, is easy to implement in hardware, and is extended to provide similar properties when a module failure occurs.
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