Importance

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Abstract

A PWM type D/A converter having a first PWM converter, a second PWM converter and an analog adder. The digital input signals are designated as odd and even numbered input signals and the reference timing points for outputting odd/even numbered input signal are designated as odd/even numbered reference timing points. The first PWM converter receive the digital input signal to output signal whose rising/falling timing point is set at the earlier/later timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by the values of the odd numbered input signal and the next even numbered input signal. The second PWM converter receives the digital input signal to output signal whose rising/falling timing point is set at the later timing, the larger the value of the even/odd numbered input signal relative to the even/odd numbered reference timing point and the pulse width is determined by the value of the even numbered input signal and the next odd numbered input signal. In another aspect the second PWM converter receives the digital input signal to output signal whose rising/falling timing point is at the later the timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by complementary values of the odd numbered input signal and the next even numbered input signal.

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First Claim