Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 23, 1991
Issued Date -
N/A
app pub date -
Oct 5, 1989
filing date -
May 1, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing titanium metal everywhere, and then heating the integrated circuit structure in a nitrogen atmosphere. This process may also be used with other refractory metal nitride interconnect layers. In addition to titanium based thin film compositions, other metals can be substituted and used for direct-react silicidation and simultaneous formation of a conductive nitride to form local interconnects, including molybdenum, tungsten, vanadium, cobalt, and others.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully