System for synchronizing data frames in a serial bit stream
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United States of America Patent
Stats
-
Apr 23, 1991
Grant Date -
N/A
app pub date -
Jun 30, 1989
filing date -
Jun 30, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A synchronizer in a receiver for a serial data stream includes a shift register for temporarily storing the most recently received data. Taps at a plurality of locations on such shift register provide bit signals at regularly spaced locations. These bit signals are checked for the occurrence of predetermined patterns which indicate the occurrence of frame bit candidates. A candidate shift register indicates which bit positions currently remain as candidates for the frame bit position, and is shifted synchronously with the incoming data. The candidate shift register is N bits in length, and a modulo-N counter is connected to the serial output thereof. Each time a bit position shifted out of the candidate register contains a valid candidate, the modulo-N counter is reset. When the counter counts for a full cycle, the true frame bit position has been identified.
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