Method for parallel testing of semiconductor devices
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United States of America Patent
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Apr 30, 1991
Grant Date -
N/A
app pub date -
Nov 3, 1989
filing date -
Nov 3, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method of testing unpackaged integrated circuits using a tester which is capable of testing a plurality of memories in parallel is provided. A membrane test head having a plurality of probe bumps thereon is provided wherein the probe bumps are coupled to the tester by microstrip transmission lines formed on the membrane test head. The semiconductor memory has a plurality of contact pads thereon which are coupled to the probes. In this manner, a plurality of semiconductor memories can be tested in wafer form. Alternatively, individual semiconductor memory chips can be mounted on a receiver plate and tested individually or in parallel by moving the receiver plate so that the contact pads couple to the probes.
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