Digital PLL circuit having reduced lead-in time
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United States of America Patent
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Apr 30, 1991
Grant Date -
N/A
app pub date -
Sep 27, 1989
filing date -
Sep 29, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A digital PLL circuit to output a clock signal phase-synchronized with an input signal comprises a divider outputting the clock signal and a signal initiation pulse generator generating a signal to set the divider to a predetermined state depending on the input signal initiation. The maximum lead-in time is reduced to 1/n in comparison with prior art, and therefore the circuit is very suitable for use in the receiving part of a device which receives a burst data signal.
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