Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5012323
SERIAL NO

07439243

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Abstract

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A semiconductor package incorporating a pair of semiconductor dice on a single leadframe of the type having a wire-bonding region at each end of a die-attachment region which has both an upper and lower surface. The first of said pair of dice is back bonded to the upper surface of said die-attachment region; the second is face bonded to the lower surface of said die-attachment region. Electrical interconnections between said second die and said leadframe pass through an aperture in the leadframe. The dual-die package can be used to approximately double circuit density in a number of different packages, including a dual inline package (DIP), a small-outline J-lead package (SOJ), a single inline package (SIP), zig-zag inline package (ZIP), and other variations of the single- and double-row inline-lead packages.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INC IDAHO A CORP OF DE2805 E COLUMBIA ROAD BOISE ID 83706

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farnworth, Warren M Nampa, ID 855 33798

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