Method and apparatus for calibrating linear delay lines
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United States of America Patent
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May 7, 1991
Grant Date -
N/A
app pub date -
Sep 21, 1989
filing date -
Sep 21, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A circuit for calibrating linear delay lines wherein a periodic ramp voltage is counted a fixed number of times at first and second frequencies. While the ramp voltages are being counted at each frequency, system clock pulses are counted. The number of system clock pulses counted for each first and second ramp voltage frequency is used to adjust the charging current applied to an integrator which establishes the delay value.
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