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Abstract

A circuit for asynchronously delaying an input signal whereby the precision of the time delay is proportional to the precision of the clock. A first circuit is coupled across a first capacitor for charging the first capacitor to a predetermined voltage when the clock is in a first logic state and discharging the first capacitor when the clock is in a second logic state. A peak-hold circuit having an input coupled to a first terminal of the first capacitor and an output signal at an output that provides a reference voltage representative of the peak voltage occurring at the input of the peak-hold circuit which is a function of the time interval the clock occupied the first logic state. A second circuit is coupled across a second capacitor for charging the second capacitor when the input signal is in a first logic state, and discharging the second capacitor when the input signal is in a second logic state. Also, a comparator having a first input coupled to the output of the peak-hold circuit, a second input coupled to a first terminal of the second capacitor, and an output at which an output signal is provided that represents the input signal delayed by a predetermined time which is a function of the reference voltage.

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First Claim