Importance

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Abstract

A data processor includes a bus interface coupled to an external bus for transferring information to and from the external bus, an instruction decoding section coupled to the bus interface to receive an instruction through the bus interface from the external bus to decode the received instruction, and an instruction execution unit coupled to receive decoded information from the instruction decoding section to execute the received decoded information. The instruction decoding section includes an instruction decoder receiving an instruction through the bus interface to output the decoded information to the instruction execution unit and to generate tag information, an effective address generator receiving the tag information to calculate an effective address, and a memory management unit receiving the effective address to generate a real address. When the tag information indicates that the decoded information is a predetermined input/output instruction, the memory management unit controls the bus interface to limit data transfer between the external bus and the bus interface until a predetermined condition is satisfied.

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First Claim