Low jitter DDFS FSK modulator
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United States of America Patent
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-
May 14, 1991
Grant Date -
N/A
app pub date -
Mar 3, 1989
filing date -
Mar 3, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A low jitter direct digital frequency synthesized frequency shift keyed modulator has a tapped delay line to provide polyphase sampling of an asynchronous data input signal. The samples from the tapped delay line are input to a correction signal generator that produces a correction signal as a function of the location of data transitions in the data input signal with respect to a specified point of a sample clock pulse. The correction signal is used to offset a modulating input to a direct digital frequency synthesizer so that the frequency shift keyed output reflects the data transitions within 1/n of the period of the sample clock pulse.
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