Method and apparatus for DRAM memory performance enhancement
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United States of America Patent
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Jun 4, 1991
Grant Date -
N/A
app pub date -
Oct 28, 1988
filing date -
Oct 28, 1988
priority date (Note) -
Expired
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Abstract
A method and apparatus is disclosed for improving the performance of a digital computer by reducing the latency of read operations and increasing available write bandwidth by utilizing a subset of the address bits which are the same from one operation to the next. A faster cycle type (e.g. page mode or static column) can thereby be employed in the Dynamic Random Access Memory (DRAM) memory by eliminating the DRAM precharge and RAS address portions of the cycle.
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