Architecture of high speed synchronous state machine
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United States of America Patent
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Jun 11, 1991
Issued Date -
N/A
app pub date -
Oct 31, 1989
filing date -
Sep 2, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An improved architecture for and a method of operating a high speed synchronous state machine is disclosed having a programmable logic array receiving inputs from dedicated input registers and having an input/output macrocell which includes two state registers and two input registers, and two transparent latches and two feedback multiplexers. The outputs from the input registers are multiplexed through an input multiplexer and the input registers may be clocked at different input clock rates than the state clock which clocks the state registers.
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