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Abstract

A bit serial multiplier suitable for pipelined operations. This multiplier uses a conventional bit serial multiplier cell using Booth's algorithm and stored carry architecture, but modified in several respects. First, the partial product and carry storage registers may be put in a hold state so that their contents remain constant over as many clock cycles as a stall signal is asserted so that data may be inserted in the pipeline without destroying pipeline synchronization. Second, there are added two shift registers one of which parallel loads the partial product bits and the other of which loads the carry bits as each set of bits exists after all the multiplier bits have been shifted into the multiplier. After the parallel loading process, the partial product and carry latches in the main cell are cleared thereby allowing another multiplication with different operands to begin. While this second multiplication is being performed, the partial product and carry bits from the first multiplication are being shifted out of the shift registers to an adder which combines these bits to derive the final product bits. Multiple multiplicand storage registers are provided for allowing prefetch and rapid change of operands and multiple multiplier bit stream control circuitry is provied.

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First Claim