Importance

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Abstract

A single port dual RAM comprising, on a single chip, at least one storage array including a plurality of hierarchical bit lines which serve as the interconnecting path between dynamic type storage elements for main memory and static type storage elements for cache memory. Each of said storage array(s) includes an input/output port for selective access to the storage array. Each hierarchical bit line includes a DRAM bit line, a SRAM bit line and interface means for electrically interconnecting the DRAM bit line to the SRAM bit line or isolating the DRAM bit line from the SRAM bit line. A SPDRAM chip which shares typical DRAM peripheral circuitry may be employed in a distributed on-chip cache to enlarge the data transfer width in a simple structure.

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First Claim