US Patent No: 5,026,666

Number of patents in Portfolio can not be more than 2000

Method of making integrated circuits having a planarized dielectric

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Abstract

An integrated circuit is made by a technique that provides a planar dielectric over gate, source, and drain regions without over-etching of the gate contact region, In the inventive process, the contact windows are etched in the conformal dielectric prior to the planarization step, so that the etch thickness is the same for the gate as for the source/drain windows. Then, a sacrificial planarizing polymer (e.g., a photoresist) is deposited to cover the conformal dielectric and fill the etched windows. Finally, a planarizing etch-back is performed, and the polymer is removed from the contact windows. A planarized dielectric is achieved without excessive etching of the gate windows.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
AMERICAN TELEPHONE AND TELEGRAPH COMPANYMURRAY HILL, NJ3140
AT&T BELL LABORATORIESMURRAY HILL, NJ3373

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hills, Graham W Los Gatos, CA 11 381
Huttemann, Robert D Macungie, PA 5 109
Olasupo, Kolawole R Kutztown, PA 3 66

Cited Art

Patent Info (Count) # Cites Year
 
ADVANCED MICRO DEVICES, INC. (1)
4,481,070 Double planarization process for multilayer metallization of integrated circuit structures 18 1984
 
Bell Telephone Laboratories, Incorporated (1)
4,933,297 Method for etching windows having different depths 16 1989
 
LSI LOGIC CORPORATION (1)
4,879,257 Planarization process 74 1987
 
MOTOROLA, INC. (1)
4,740,483 Selective LPCVD tungsten deposition by nitridation of a dielectric 21 1987
 
NEC CORPORATION (1)
4,868,137 Method of making insulated-gate field effect transistor 32 1988
 
NORTEL NETWORKS LIMITED (1)
4,601,781 Method for improving step coverage of dielectrics in VLSI circuits 16 1984
 
Signetics Corporation (1)
4,708,767 Method for providing a semiconductor device with planarized contacts 14 1984
 
TEXAS INSTRUMENTS INCORPORATED (1)
4,657,628 Process for patterning local interconnects 75 1986
 
THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY (1)
4,888,087 Planarized multilevel interconnection for integrated circuits 17 1988

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (11)
5,206,187 Method of processing semiconductor wafers using a contact etch stop 49 1991
5,387,550 Method for making a fillet for integrated circuit metal plug 35 1992
6,680,255 Plasma etching methods 1 1999
6,478,978 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 1 2000
6,479,393 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 0 2000
7,183,220 Plasma etching methods 0 2000
6,533,953 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 3 2001
6,660,644 Plasma etching methods 0 2001
6,967,170 Methods of forming silicon nitride spacers, and methods of forming dielectric sidewall spacers 0 2002
6,800,561 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 1 2002
6,878,300 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 3 2002
 
KABUSHIKI KAISHA TOSHIBA (5)
5,529,953 Method of forming studs and interconnects in a multi-layered semiconductor device 58 1994
5,602,050 Method of making a semiconductor device with conductors on stepped substrate having planar upper surfaces 4 1995
5,689,140 Method for forming studs and interconnects in a multi-layered semiconductor device 24 1996
6,124,189 Metallization structure and method for a semiconductor device 62 1997
5,883,006 Method for making a semiconductor device using a flowable oxide film 59 1997
 
SAMSUNG ELECTRONICS CO., LTD. (5)
5,455,192 Method of making dynamic random access memory cell having a stacked capacitor and a trench capacitor 13 1991
5,622,883 Method for manufacturing semiconductor memory device having landing pad 31 1995
6,117,766 Method of forming contact plugs in a semiconductor device 3 1998
6,146,994 Method for forming self-aligned selective silicide layer using chemical mechanical polishing in merged DRAM logic 12 1999
7,078,771 SOI structure and method of producing same 2 2003
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (4)
5,112,765 Method of forming stacked tungsten gate PFET devices and structures resulting therefrom 57 1991
5,573,633 Method of chemically mechanically polishing an electronic component 42 1995
5,940,729 Method of planarizing a curved substrate and resulting structure 15 1996
6,150,255 Method of planarizing a curved substrate and resulting structure 5 1999
 
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (3)
5,380,680 Method for forming a metal contact of a semiconductor device 10 1993
5,461,004 Method for fabricating connection device with reduced area of highly integrated semiconductor device 16 1993
5,595,936 Method for forming contacts in semiconductor device 3 1995
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (3)
5,180,689 Tapered opening sidewall with multi-step etching process 42 1991
6,703,187 Method of forming a self-aligned twin well structure with a single mask 2 2002
6,743,715 Dry clean process to improve device gate oxide integrity (GOI) and reliability 0 2002
 
FREESCALE SEMICONDUCTOR, INC. (2)
5,275,973 Method for forming metallization in an integrated circuit 33 1993
6,566,264 Method for forming an opening in a semiconductor device substrate 3 2000
 
LSI LOGIC CORPORATION (2)
5,472,901 Process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps 28 1994
5,663,590 Product of process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps 16 1996
 
RENESAS ELECTRONICS CORPORATION (2)
5,575,886 Method for fabricating semiconductor device with chemical-mechanical polishing process for planarization of interlayer insulation films 9 1995
5,677,243 Method of forming multi-layer interconnection 19 1996
 
SONY CORPORATION (2)
6,218,266 Method of fabricating electronic devices of the type including smoothing process using polishing 7 1992
5,502,008 Method for forming metal plug and/or wiring metal layer 21 1994
 
STMICROELECTRONICS, INC. (2)
6,297,110 Method of forming a contact in an integrated circuit 2 1994
6,580,133 Contact in an integrated circuit 1 2001
 
APPLIED MATERIALS, INC. (1)
5,288,665 Process for forming low resistance aluminum plug in via electrically connected to overlying patterned metal layer for integrated circuit structures 49 1992
 
AT&T IPM CORP. (1)
5,461,005 Method of forming silicide in integrated circuit manufacture 1 1991
 
BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM (1)
5,292,558 Process for metal deposition for microelectronic interconnections 65 1991
 
GLOBALFOUNDRIES INC. (1)
5,705,430 Dual damascene with a sacrificial via fill 108 1995
 
HEWLETT-PACKARD COMPANY (1)
5,223,084 Simultaneous dielectric planarization and contact hole etching 9 1991
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
6,372,641 Method of forming self-aligned via structure 1 1996
 
LUCENT TECHNOLOGIES INC. (1)
5,880,022 Self-aligned contact window 3 1991
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
5,916,820 Thin film forming method and apparatus 8 1995
 
MITSUBISHI DENKI KABUSHIKI KAISHA (1)
6,455,410 Semiconductor device and method of manufacturing the same 3 2001
 
NEC ELECTRONICS CORPORATION (1)
5,595,937 Method for fabricating semiconductor device with interconnections buried in trenches 101 1996
 
UNITED MICROELECTRONICS CORP. (1)
6,156,642 Method of fabricating a dual damascene structure in an integrated circuit 12 1999
 
WINBOND ELECTRONICS CORP. (1)
5,854,124 Method for opening contacts of different depths in a semiconductor wafer 3 1997