Importance

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Abstract

The wafer scale integrated circuit comprises an array of undiced chips or modules, each of which includes a data storing or processing circuit, e.g. a dynamic RAM, and configuration logic. Channels for data and control signals exist between each module and its (N, S, E and W) neighbors and a target module in the array may be addressed by setting up a path through the array from an entry module to the target module. The addressing is effected by sending a stream of link commands, each of which tells a module to link on to its (N, S, E or W) neighbor. Each module responds to the first command of the stream and then sends on the stream stripped of this first command. In an alternative embodiment the link commands are transmitted from module to module in parallel, each module responds to the command at the least significant end and strips it off by a shift of the commands in the least significant direction before the commands pass to the next module. A control circuit for addressing modules in the array at random forms a unique set of link commands for each module to be addressed, these command sets being such that the paths to the various modules form a densely branching tree commencing from the entry module.

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First Claim