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Abstract

An image processing apparatus having an image output device for delivering a mask image signal and a contrast image signal corresponding to a mask image and contrast image, and having a subtraction processor for out-putting a subtraction image signal resulting from the subtraction of the mask image signal from the contrast image signal. The mask image signal and subtraction image signal are stored in corresponding frame memories, respectively. A divider divides the mask image signal, which has been stored in the frame memory, by a constant, producing a level-down mask image signal output. An adder adds together the level-down mask image signal and the subtraction image signal to obtain a landmark image signal. A display section, upon receipt of the landmark image signal, displays, in a superimposed fashion, a subtraction image against the background of a thin mask image.

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First Claim