Semiconductor pin device with interlayer or dopant gradient

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United States of America Patent

PATENT NO 5032884
SERIAL NO

07477138

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Abstract

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A semiconductor device comprising a pin-type or nip-type amorphous-containing semiconductor layers; characterized in that (1) at least one interlayer made of semiconductor or insulator having higher electrical resistivity than a semiconductor which adjoins the interlayer is/are interposed between semiconductor layers or between a semiconductor and an electrode, (2) an amount of dopant in a p-type or n-type layer is least at a junction interface of p/i or n/i and increases gradually toward a junction interface of p/electrode or n/electrode, or (3) a p-type semiconductor layer being the same conductive type as the p-type semiconductor and having higher impurity density and/or an n-type semiconductor layer being the same conductive type as the n-type semiconductor layer and having higher impurity density is/are interposed between the p-type semiconductor layer and the electrode at the side of the p-type semiconductor layer and/or between the n-type semiconductor layer and the electrode at the side of the n-type semiconductor layer. According to the semiconductor device of the present invention (in the case of (1) or (2)), large Voc and electric current at a specific voltage can be obtained, further in the case of (3), photoelectric conversion efficiency can be improved.

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Patent Owner(s)

  • KANEGAFUCHI KAGAKU KOGYO KABUSHIKI KAISHA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Asaoka, Keizou Kobe, JP 1 25
Hiroe, Akihiko Kobe, JP 12 117
Kondo, Masataka Kobe, JP 37 711
Nishimura, Kunio Kyoto, JP 43 685
Tawada, Yoshihisa Kobe, JP 54 983
Tsuge, Kazunori Kobe, JP 54 1112
Yamagishi, Hideo Kobe, JP 32 553
Yamaguchi, Minori Akashi, JP 21 187

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