Computer system including a page mode memory with decreased access time and method of operation thereof
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United States of America Patent
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-
Jul 23, 1991
Grant Date -
N/A
app pub date -
May 26, 1988
filing date -
May 26, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A computer system is provided in which memory access time is substantially reduced. After row address strobe (RAS) and column address strobe (CAS) signals are used to select a particular address in a memory during a first memory cycle, the addressed data is latched for later transfer to a data bus. A CAS precharge of the memory is then conducted after such latching and prior to the end of the first memory cycle before the commencement of the second memory cycle.
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