Importance

Loading Importance Indicators...

Abstract

In a single instruction multiple data synchronous processor, each slave processor of an array includes a computational element and an isolated slave memory. Instructions broadcast to the slave processors may be processed simultaneously with data transfers between slave memories through communications registers and between the slave memories and an I/O processor through I/O registers. A multiplexer in each slave processor selects as an input to the communications register a signal from an adjacent slave or a nonadjacent slave to bypass a column in the array. Broadcast instructions may be overridden by individual slave processors by conditional instructions which set the otherwise unused program counter of the computational element. An array master, communication master and input/out processor may process respective sets of instructions in parallel, each addressing slave memories through a common memory controller. Code handled by the array master may be separated into control code processed by the array master and computation code broadcast to the slave processors by a translator. An incremental addressing scheme is provided. The translator may unroll one type of loop instruction to provide straight-line code processed by the slave processors or may retain loop instructions for processing as control code in the array master.

Loading the Abstract Image...

First Claim