Importance

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Abstract

A parallel clocked latch circuit having a plurality of inputs and first and second outputs includes a gate circuit responsive to the plurality of inputs for providing first and second logic output signals which are coupled to the first and second outputs of the parallel clocked latch circuit, respectively. A regeneration circuit responsive to the first and second logic output signals for storing logic levels at the first and second outputs of the latch circuit. A level shifting circuit coupled to the gate circuit for providing a predetermined voltage level shift of the logic levels of the gate circuit. A field-effect transistor having a drain coupled to the regeneration circuit, a gate coupled to a control signal, and a source coupled to a lowest level of the gate circuit, the control signal having a first logic state voltage level greater than the voltage level of a first logic state of the gate circuit by a predetermined voltage such that when the control signal is in a first logic state the regeneration circuit is rendered operative and the gate circuit is rendered non-operative. Also, a current source coupled between the source of the field-effect transistor and a first supply voltage terminal.

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First Claim