Memory accessing switch network
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United States of America Patent
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Aug 20, 1991
Grant Date -
N/A
app pub date -
Nov 30, 1988
filing date -
Nov 30, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In parallel processing computational apparatus, a switching network employing both routing switch elements and concentrator elements efficiently couples bit serial messages from a multiplicity of processors to a multiplicity of memory modules. The apparatus operates in a highly synchronous mode in which all processors issue memory requests only at essentially the same predetermined time within a frame interval encompassing a predetermined substantial number of clock periods. The routing switch elements and concentrator elements incorporate circuitry for comparing the addresses of requests which may be blocked at any element with requests which get through and, if the addresses are the same, returning the memory response to all processors seeking the same memory location.
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