Ferroelectric capacitor and memory cell including barrier and isolation layers

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United States of America Patent

PATENT NO 5046043
SERIAL NO

07105578

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Abstract

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A ferroelectric capacitor structure is designed for fabrication together with MOS devices on a semiconductor substrate. The ferroelectric capacitor includes a diffusion barrier layer above the surface of the substrate for preventing the materials of the ferroelectric capcacitor from contaminating the substrate or MOS devices. The ferroelectric capacitor comprises a bottom electrode, a thin film ferroelectric layer and a top electrode. An interlayer dielectric is formed to cover portions of the ferroelectric thin film and provide an opening therethrough for the top electrode. A ferroelectric memory cell comprises a field effect transistor together with a ferroelectric capacitor fabricated on a semiconductor substrate. In one configuration, the ferroelectric capacitor is offset from the field effect transistor, while in another configuration, the ferroelectric capacitor is substantially above the field effect transistor to provide greater density.

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Patent Owner(s)

Patent OwnerAddress
NATIONAL SEMICONDUCTOR CORPORATION A CORP OF DE2900 SEMICONDUCTOR DR SANTA CLARA CA 95052-8090

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Evans, Joseph T Albuquerque, NM 6 240
Kinney, Wayne I Albuquerque, NM 40 968
Miller, William D Rio Rancho, NM 57 2702
Shepherd, William H Corrales, NM 16 1319

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