Circuit arrangement for verifying data stored in a random access memory
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United States of America Patent
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-
Sep 3, 1991
Grant Date -
N/A
app pub date -
Feb 2, 1990
filing date -
Feb 10, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A circuit arrangement comprising, for each bit location in a column of a RAM, an input shift register, a multiplexer and a comparator. The input data bit is stored in the shift register, and the multiplexer is arranged during a write cycle, to write the data bit into a bit position. During a verification cycle, the multiplexer is arranged to write the inverse data bit into the same position, and the comparator compares the output bit position of the RAM with the inverse data bit. The result is stored in the shift register, which can be down-loaded for analysis.
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