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Abstract

A converter circuit for converting binary logic signals from a CMOS circuit into binary signals for an ECL circuit. Two output transistors in the converter circuit are connected in parallel between the V.sub.DD CMOS supply voltage and the output of the converter circuit. The resistance across the drain-to-source terminals of the output transistors form a voltage divider network with a pulldown resistor in the ECL circuit. In one embodiment, one of the output transistors is enabled by a logic '1' from the CMOS circuit and the other is enabled only by a logic '0'. In another embodiment, one output transistor is always enabled and the other is enabled only by a logic '0' from the CMOS circuit. In both embodiments, the effective resistance across the parallel transistors is different for a logic level '1' and a logic level '0', so that the voltage at the output is also different. The aspect ratio of the output transistors is chosen in order to obtain the desired voltages at the output which correspond to the ECL logic signals.

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First Claim