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Abstract

The present invention comprises the hardware implementation of an algorithm for a run length limited (1,7) block code of rate 2/3, wherein 2 unconstrained bits are mapped onto 3 constrained bits. The encoded data stream has a minimum of 1 'zero' between adjacent 'ones', and a maximum of seven 'zeros' between adjacent 'ones'. Unlike earlier (1,7) block encoders, the encoder of the present invention is a 4 state machine whose internal state description requires only 2 bits, rather than the 3 bits as taught in the prior art. The 4 state encoder combines the 2 incoming data bits with present state information to generate the output encoded sequence, and the next state designation. Error propagation due to a single channel bit error is limited to 5 bits. The decoder of the invention utilizes three, 3 bit shift registers which hold 9 bits of the encoded data; each group of three bits is decoded into 2 bits corresponding to the original input bits by means of a logic array fed from the three shift registers.

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First Claim