Device for synchronizing a clock in relation to an incident digital signal, in particular at high transmission rates
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United States of America Patent
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-
Sep 17, 1991
Grant Date -
N/A
app pub date -
Nov 21, 1988
filing date -
Nov 25, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The device comprises preprocessing circuitry which deliver to a phase locked loop a preprocessed signal obtained from a replica of the incident digital signal staggered in time by a fraction of the cycle of the clock signal of the phase locked loop. This device then allows a fast synchronization of the clock of the phase locked loop in relation to the incident digital signal, in particular at high transmission rates.
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