Importance

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Abstract

A microprocessor-based controller with synchronous reset including a processor for processing information having an input receiving an input signal and an output providing an output signal. The input signal conveys information about the process and the output signal controls at least one parameter related to the process. The controller includes a reset circuit for applying a reset signal to a reset terminal of the processor. The reset circuit receives a substantially constant supply signal and is responsive to reception of that supply signal to generate the reset signal, which reset signal has succeeding repetitive first and second signal levels. The processor is responsive to the reset circuit to assume an active state when the reset signal is at a first signal level and to assume an inactive state when the reset signal is at a second signal level, and the processor executes succeeding portions of a program employing the input signal program in synchrony with succeeding first signal levels of the reset signal to generate the output signal, thereby controlling the process.

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First Claim