Memory cell having means for maintaining the gate and substrate at the same potential
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United States of America Patent
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Sep 24, 1991
Grant Date -
N/A
app pub date -
Mar 23, 1989
filing date -
Mar 25, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory cell is provided comprising a bistable latch (I1, I2) having first and second nodes (NODE 1, NODE 2) and a nonvolatile transistor (NV1). The control gate of the nonvolatile transistor is connected to the first node and either the source or drain is connected to the second node. A switching transistor is provided for maintaining the control gate and the substrate of the nonvolatile transistor at substantially the same potential during volatile operation of the latch, thereby reducing voltage stress which would lead to charge tunnelling to or from the floating gate. In this way, disturbance of the floating gate charge is avoided during volatile operation. The cell is particularly suited to silicon gate fabrication technology.
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