Microprocessor having a protection circuit to insure proper instruction fetching
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United States of America Patent
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-
Oct 15, 1991
Grant Date -
N/A
app pub date -
Jun 26, 1989
filing date -
Aug 5, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A microprocessor including a CPU, an instruction memory (ROM) with a sequencer in the CPU that sends out a fetch signal for an instruction, and an address decoder that decodes the fetch signal and sends a signal to the ROM allowing the fetch signal to fetch an instruction if the address is correct.
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