CMOS amplifier with offset adaptation

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United States of America Patent

PATENT NO 5059920
SERIAL NO

07525764

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. An analog MOS integrated circuit comprises an amplifier circuit having a gain much larger than 1. The inverting input into one stage of this amplifier circuit is a floating node forming the gate of at least one MOS transistor. A first capacitor couples an input of the circuit to this floating node. Electrical semiconductor structures are provided for both linearly adding and removing charge from the floating gate, thus allowing the offset voltage of the amplifier to be adapted. An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An electrical learning means allows the floating node to be charged or discharged to a voltage which effectively cancels the input offset voltage.

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Patent Owner(s)

Patent OwnerAddress
SYNAPTICS INC A CA CORP2860 ZANKER RD STE 105 SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Allen, Timothy P Los Gatos, CA 62 16784
Anderson, Janeen D W Fremont, CA 13 1670
Mead, Carver A Pasadena, CA 81 7971
Wall, Michael F Sunnyvale, CA 9 1113

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