Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider
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United States of America Patent
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Oct 22, 1991
Issued Date -
N/A
app pub date -
Apr 26, 1990
filing date -
Nov 7, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A phase locked loop configured as a frequency multiplier capable of nonintegral feedback path division utilizes a multiphase voltage controlled oscillator (5) which generates a plurality of signals (10a-10f) having a substantially identical frequency but each offset equally from the other by a given phase angle. A commutator (3) selects signals of adjacent phases so as to give the time average output signal (9) a frequency higher or lower than the frequency 10a-10f. Frequency translation is accomplished by periodically selecting signals having a longer or shorter period as desired so that a commutator output signal (9) is delayed or advanced by an appropriate amount. In the preferred embodiment, the phase locked loop is capable of converting a 1.544 MHz signal to a 2.048 MHz signal or vice versa.
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