Computer display controller with reconfigurable frame buffer memory
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United States of America Patent
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-
Oct 29, 1991
Grant Date -
N/A
app pub date -
Dec 9, 1988
filing date -
Dec 9, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A computer display controller (50) cooperates with a host microprocessor (18) to direct display data to a frame buffer memory (16) in accordance with a selected one of multiple frame buffer memory configurations (20 and 30). The display controller includes an address decoder circuit (58) that delivers address information generated by the host microprocessor to the address inputs (64) of the frame buffer memory in accordance with the selected frame buffer memory configuration.
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