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Abstract

An ATM (asynchronous transfer mode) exchange system for high speed packet exchange with a fixed length packet is implemented by a plurality of cell handlers (10-1 through 10-n) each related to each ATM channel, and a plurality of buses coupled with the cell handlers. An input user cell is subject to add routing information including an output cell handler number (403) and an output virtual channel identifier (404) by a virtual channel converter (12) and a routing header adder (13). The user cell which has routing information is forwarded to the bus. The cell on the bus is read out by all the cell handlers, and the particular cell handler in which the number of cell handlers coincide with the cell handler number in routing information takes the cell on the bus. In the cell handler, the cell itself read out of the bus is stored in the cell buffer memory (16), and the address of the cell buffer memory (16) of the cell is stored in the queue buffer (18). When an output channel is available, the cell is forwarded to the output channel from the cell buffer memory (16) based upon the address of the cell stored in the queue buffer (18). A plurality of queue buffers may be provided for delay time control. Congestion control is possible for loss control of a cell when an output channel is congested, based upon the number of cells waiting in the queue buffer.

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