Amorphous silicon thin film transistor array substrate and method for producing the same

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United States of America Patent

PATENT NO 5065202
SERIAL NO

07534003

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Abstract

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An amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, as gate wiring itnerconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of the source wiring. In the process for forming the array, the gate insulating layer is formed in a portion of the structure other than the terminal part of the gate, and the terminal part of the source wiring is formed on the gate insulating layer.

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Patent Owner(s)

Patent OwnerAddress
SEIKO PRECISION INCCHIBA COUNTY JAPAN CHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tanaka, Sakae Tokyo, JP 100 877
Watanabe, Yoshiaki Tokyo, JP 193 2642

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