Apparatus for providing block erasing in a flash EPROM

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United States of America Patent

PATENT NO 5065364
SERIAL NO

07407645

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Abstract

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A flash EPROM memory array having vertical blocking is described. The array is organized into a plurality of vertical (column) blocks. Each block includes a source region switch which couples all the source regions in the memory cells in its respective block to a programming potential, ground or a disturb inhibit potential. Each of the blocks may be erased without disturbing the programming in the other blocks.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION 3065 BOWERS AVENUE SANTA CLARA CA 95051 A CORP OF DEDE

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Atwood, Gregory E San Jose, CA 31 2563
Fazio, Albert Los Gatos, CA 36 2321
Lodenquai, Richard A San Jose, CA 1 175

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