Non-volatile RAM bit cell
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United States of America Patent
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Nov 12, 1991
Grant Date -
N/A
app pub date -
Jul 17, 1990
filing date -
Jul 13, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory cell comprising a bistable latch having first and second nodes, at least two non-volatile transistors (NV1, NV2) each having a source, a drain and a control gate, the control gates being connected to the first node (NODE 1) and one of the source and drain of each transistor being connected to the second node (NODE 2), each non-volatile transistor (NV1, NV2) further having a substrate and a floating gate between the control and the substrate, and switching means (N1, N2, TG1) for enabling the transistors to be checked in circuit.
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