Process monitor circuit
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United States of America Patent
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-
Nov 26, 1991
Grant Date -
N/A
app pub date -
Sep 5, 1990
filing date -
Sep 5, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In accordance with the present invention, a process monitor circuit and a method for monitoring a process are provided. The process monitor circuit provides first and second logic paths, the first logic path having a delay sensitive to whether the input logic transition is from logic high to logic low, or from logic low to logic high. The second logic path has substantially equal delays for either logic state transition. The two differences in delay between the first and second logic paths under the two logic state transitions are used to monitor the process steps for manufacturing the P and N transistors.
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